1. Field of the Invention
Embodiments of the invention relate to phase detectors. More particularly, embodiments of the invention relate to linear phase detectors used for data recovery.
2. Discussion of Related Art
In general, clock/data recovery circuits (CDRs) are used to provide clocks necessary for recovering digital signals at receiving stages of high-frequency data communication systems such as optical communication systems, backplane routing systems, or chip-to-chip interconnection systems. Depending on whether or not a reference clock is provided from an external crystal oscillator, CDR structures may be differentiated into a recovering clock without using a reference clock and a recovering clock using a reference clock. A recovering clock that does not use a reference clock extracts frequency information directly from input data by means of a frequency detector. A recovering clock which utilizes a reference clock generates a clock of the same frequency with a bit rate of input data via the external clock and a clock divider.
A phase detector (PD) determines the operation speed of the CDR. The phase detector must be operable in high speeds for detecting a phase difference between data and the clock. Typical phase detectors include linear and binary detectors both of which effect overall operating characteristics. In particular, a linear phase detector detects phase incline as early phase or late phase. However, a linear phase detector is unable to use multiple phases requiring system circuits to operate at the same rate with input data. For example, when recovering data of 10 Gbps, there is an operational burden of operating all circuits including the phase detector at a rate suitable for the data rate of 10 Gbps. Therefore, it is not easy to implement a linear phase detector suitable for a CDR requiring a high operation rate.
A nonlinear phase detector operates to detect whether a phase is early or late. A binary phase detector only detects the direction of a phase error regardless of its size. Consequently, when input data has associated jitters, the response characteristic of the system varies. Additionally, a nonlinear phase detector is incapable of conducting an analyzing operation by a linear time-invariant (LTI) as compared with a linear phase detector. This is because an output voltage of the phase detector is operable in a nonlinear characteristic making it difficult to determine operational characteristics of the entire circuit in design.
The number of operating times of a charge pump is smaller in the linear phase detector as compared to the nonlinear phase detector. This reduces the number of ripples of a control voltage from a voltage-controlled oscillator (VCO). Thus, the linear phase detector is advantageous for input data having low jitters. Most phase detectors employ differential exclusive logic circuits for detecting error signals corresponding to phase differences between data and clock signals. A detected error signal has a smaller signal width than a unit interval (UI). Phase detectors employing such a differential exclusive logic circuit have error signals with smaller signal widths. These signal widths are several tens to several ps smaller than 100 ps as the data rate increases over 10 Gb/s. Because of these smaller signal widths it may be unable to detect such a small error signal via a differential exclusive logic circuit. Therefore, an operation rate of a CDR is restricted by the operation rate of the differential exclusive logic circuit.